
-- VHDL Instantiation Created from source file clocking_temp.vhd -- 19:36:21 03/03/2014
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT clocking_temp
	PORT(
		CLK_IN : IN std_logic;          
		CLK_PIXEL : OUT std_logic;
		CLK_TMDS0 : OUT std_logic;
		CLK_TMDS90 : OUT std_logic
		);
	END COMPONENT;

	Inst_clocking_temp: clocking_temp PORT MAP(
		CLK_IN => ,
		CLK_PIXEL => ,
		CLK_TMDS0 => ,
		CLK_TMDS90 => 
	);


